Semiconductor integrated circuit device and communication system

ABSTRACT

According to an embodiment, a semiconductor integrated circuit device includes an amplifier and a feedback circuit. The amplifier includes an input terminal receiving an input signal and an output terminal outputting an output signal. The feedback circuit includes a first transistor generating a bias current. The feedback circuit is configured to operate based on the bias current. The feedback circuit is configured to receive the output signal to supply a feedback signal to the input terminal. A signal having a reverse phase to the output signal is input to a gate of the first transistor.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2010-52965 filed on Mar. 10,2010 in Japan, the entire contents of which are incorporated herein byreference.

FIELD

Embodiments described herein relate generally to a semiconductorintegrated circuit device and a communication system.

BACKGROUND

As configurations of a low noise amplifier with broadband inputmatching, there are a resistive termination configuration, a common gateconfiguration, a resistor feedback configuration, and an active feedbackconfiguration. Among these, the active feedback configuration using acommon drain circuit is advantageous in noise, band width, and area andeasily benefits from process miniaturization, and thus there is a highpossibility that it will be widely used in the future.

In the common drain feedback low noise amplifier, a common drain circuitas a feedback path is connected between an input and an output of theamplifier (for example, see WO/2008/142051 Pamphlet). Since the commondrain circuit is connected to the input, a bandwidth of input matchinggets narrowed by a parasitic capacitance (an input capacitance) causedby the common drain circuit. The common drain circuit also acts as anoise source.

However, in the conventional common drain feedback low noise amplifier,it is difficult to reduce the input capacitance and the noise.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a low noise amplifier according to acomparative example.

FIG. 2 is a circuit diagram illustrating a configuration of a low noiseamplifier according to the comparative example.

FIG. 3 is a block diagram of a system using a low noise amplifieraccording to a first embodiment of the present invention.

FIG. 4 is a circuit diagram of the low noise amplifier according to thefirst embodiment of the present invention.

FIG. 5 is a circuit diagram of a low noise amplifier according to asecond embodiment of the present invention.

FIG. 6 is a circuit diagram of comparative circuits of the low noiseamplifier according to the second embodiment of the present inventionand the low noise amplifier according to the comparative example.

FIG. 7 is a view illustrating characteristics of the low noise amplifieraccording to the second embodiment of the present invention and the lownoise amplifier according to the comparative example.

FIG. 8 is a circuit diagram of the low noise amplifier according to amodification of the first embodiment.

FIG. 9 is a circuit diagram of the low noise amplifier according to amodification of the second embodiment.

FIG. 10 is a circuit diagram of a single ended to differentialconversion circuit and a low noise amplifier according to a thirdembodiment of the present invention.

FIG. 11 is a circuit diagram of a single ended to differentialconversion circuit and a low noise amplifier according to a fourthembodiment of the present invention.

FIG. 12 is a circuit diagram of a single ended to differentialconversion circuit and a low noise amplifier according to a fifthembodiment of the present invention.

FIG. 13 is a circuit diagram of a single ended to differentialconversion circuit and a low noise amplifier according to a sixthembodiment of the present invention.

DETAILED DESCRIPTION

According to an embodiment, a semiconductor integrated circuit deviceincludes an amplifier and a feedback circuit. The amplifier includes aninput terminal receiving an input signal and an output terminaloutputting an output signal. The feedback circuit includes a firsttransistor generating a bias current. The feedback circuit is configuredto operate based on the bias current. The feedback circuit is configuredto receive the output signal to supply a feedback signal to the inputterminal. A signal having a reverse phase to the output signal is inputto a gate of the first transistor.

Before describing embodiments of the present invention, a common drainfeedback low noise amplifier (hereinafter, referred to as “low noiseamplifier”) of a comparative example, known to the inventor of thepresent application, will be described.

FIG. 1 is a circuit diagram of a conventional and general low noiseamplifier according to a comparative example. The low noise amplifieramplifies an input signal V_(in) input from an input terminal with lownoise and outputs an output signal V_(out). An NMOS transistor M₁ and aload Z_(L) configure an amplifier. An NMOS transistor M₂ and a currentsource I_(bias) configure a common drain circuit. The common draincircuit supplies the input terminal with a feedback signal based on theoutput signal V_(out).

Input impedance Z_(in) of the circuit is expressed by Equation (1).Here, a parasitic capacitance is not considered.

$\begin{matrix}{Z_{in} = \frac{1}{\left( {1 + {g_{m\; 1}Z_{L}}} \right)g_{m\; 2}}} & (1)\end{matrix}$

Here, g_(m1) and g_(m2) represent mutual conductances of the NMOStransistors M₁ and M₂, respectively. In order to match the inputimpedance Z_(in) with signal source impedance R_(s), g_(m2) of the NMOStransistor M₂ whose drain is grounded is set to satisfy Equation (2).

$\begin{matrix}{g_{m\; 2} = \frac{1}{\left( {1 + {g_{m\; 1}Z_{L}}} \right)R_{s}}} & (2)\end{matrix}$

In an actual circuit, a MOS transistor is used as the current sourceI_(bias). FIG. 2 is a circuit diagram illustrating a configuration of alow noise amplifier according to a comparative example. The low noiseamplifier is different in the following points from the low noiseamplifier of FIG. 1 but is the same in the basic operation.

An NMOS transistor M_(nBias) receives a bias voltage through a gate andfunctions as a current source that supplies the NMOS transistor M_(n2)with a bias current. In the low noise amplifier, an inductor L_(LOAD) isused as a load, and an NMOS transistor M_(nCasc) is cascode-connectedbetween the inductor L_(LOAD) and a drain of an NMOS transistor M_(n1).

In the configuration of FIG. 2, an input node “in” is connected to asource of the NMOS transistor M_(n2) and a drain of the NMOS transistorM_(nBias). Since the transistor acts as the noise source, in order toreduce the noise, it is necessary to reduce the mutual conductances ofthe two NMOS transistors as much as possible. Further, the parasiticcapacitance of the input node deteriorates input matching of a highfrequency area and causes a bandwidth of input matching to be narrowed.Therefore, it is necessary to reduce the parasitic capacitance. Forthese reasons, it is necessary to reduce the sizes of the NMOStransistors M_(n2) and M_(nBias) as much as possible. However, since themutual conductance of the NMOS transistor M_(n2) is determined as inEquation (2) and an adjustment range thereof is limited, the inventor ofthe present application uniquely found out that there is a limit in arange of adjusting the sizes of the NMOS transistors M_(n2) andM_(nBias).

The inventor of the present application completed the present inventionbased on the knowledge uniquely found out above.

Hereinafter, embodiments of the present invention will be described withreference to the accompanying drawings. The present invention is notlimited to the embodiments.

First Embodiment

In the present embodiment, a signal having a phase reverse to an outputsignal is input to a gate of a transistor used as a bias current sourceof a common drain circuit as a feedback path.

First, an example of a system using a low noise amplifier will bedescribed.

FIG. 3 is a block diagram of a system using a low noise amplifieraccording to a first embodiment of the present invention. As illustratedin FIG. 3, the system includes a baseband section 1, a transceiver 2,and a front end section 3. The transceiver 2 includes a receiver 4, atransmitter 5, and a local frequency oscillator 6. The low noiseamplifier of the present embodiment is used in the receiver 4.

A receiving side operation of the system will be described. A receivingsignal of a high frequency, received by an antenna 11, is input to a lownoise amplifier (LNA) 15 through a switch 12 and a band pass filter(BPF) 13. The low noise amplifier 15 amplifies the input signal with lownoise and outputs the amplified signal. Frequency mixers 16 and 17convert the output signal of the low noise amplifier 15 to low frequencysignals based on signals from the local frequency oscillator 6. The lowfrequency signal is converted to a digital signal through a low passfilter (LPF) 18 and 19 and analog-to-digital (AD) converters 20 and 21,and then baseband-processed.

A transmitting side operation of the system will be described. In thebaseband section 1, a baseband signal is converted to an analog signalthrough digital-to-analog (DA) converters 22 and 23. The analog signalis converted to a high frequency signal in frequency mixers 26 and 27through low pass filters 24 and 25. The high frequency signal isamplified by a pre-power amplifier (PPA) 28 and then additionallyamplified by a power amplifier (PA) 29. The amplified signal istransmitted from the antenna 11 through a band pass filter 30 and theswitch 12.

FIG. 4 is a circuit diagram of the low noise amplifier according to thefirst embodiment of the present invention. As illustrated in FIG. 4, thelow noise amplifier includes an NMOS transistor M₁ (a third transistor),an NMOS transistor M₂ (a second transistor), an NMOS transistor M_(bias)(a first transistor), and a load Z_(L) (a first load).

An input terminal IN is connected to a gate of the NMOS transistor M₁, asource of the NMOS transistor M₂, and a drain of the NMOS transistorM_(bias). A source of the NMOS transistor M₁ is connected to a groundpotential VSS (a second potential), and a drain thereof is connected toan output terminal OUT, a gate of the NMOS transistor M₂, and oneterminal of the load Z_(L). The other terminal of the load Z_(L) isconnected to a power-supply potential VDD (a first potential). A drainof the NMOS transistor M₂ is connected to the power-supply potentialVDD. A gate of the NMOS transistor M_(bias) is connected to an inputterminal IN_(a), and a source thereof is connected to the groundpotential VSS.

The NMOS transistor M₁ and the load Z_(L) configure an amplifier. TheNMOS transistors M₂ and M_(bias) configure a common drain circuit (afeedback circuit).

A bias voltage is applied to the gate of the NMOS transistor M_(bias) sothat the NMOS transistors M₁, M₂, and M_(bias) can operate in asaturated region. The bias current generated by the NMOS transistorM_(bias) flows to the NMOS transistor M₂. A predetermined bias currentflows to the NMOS transistor M₁ and the load Z_(L).

The input impedance of the input terminal IN is power-matched with thesignal source impedance in a predetermined bandwidth. The input signalV_(in) input to the input terminal IN is amplified with low noise, andan output signal V_(out) is output from the output terminal OUT.

The common drain circuit receives the output signal V_(out) and suppliesthe input terminal IN with a first feedback signal. A signal having aphase reverse to the output signal V_(out) is input to the inputterminal IN_(a). The NMOS transistor M_(bias) receives the signal havingthe phase reverse to the output signal V_(out) and supplies the inputterminal IN with a second feedback signal.

As described above, in the present embodiment, the signal having thephase reverse to the signal input to the gate of the NMOS transistor M₂is input to the gate of the NMOS transistor M_(bias), and thus afeedback path having the NMOS transistor M_(bias) therein can be addedto a path having the NMOS transistor M₂ therein which is a only onefeedback path in the comparative example. Since the two feedback pathsare provided, a feedback signal increases.

The input impendence Z_(in) of the circuit of FIG. 4 can be computed asin Equation (3). Here, the parasitic capacitance is not considered.

$\begin{matrix}{Z_{in} = \frac{1}{{\left( {1 + {g_{m\; 1}Z_{L}}} \right)g_{m\; 2}} + {g_{m\; 1}Z_{L}g_{mbias}}}} & (3)\end{matrix}$

Thus, g_(m2) for matching the input impedance Z_(in) with the signalsource impedance R_(s) can be expressed as in Equation (4).

$\begin{matrix}{g_{m\; 2} = {\frac{1}{\left( {1 + {g_{m\; 1}Z_{L}}} \right)R_{s}} - {\frac{g_{m\; 1}Z_{L}}{1 + {g_{m\; 1}Z_{L}}}g_{mbias}}}} & (4)\end{matrix}$

Comparing Equation (4) with Equation (2) of the comparative example, itcan be understood that g_(m2) may be reduced by a second term ofEquation (4).

For easy understanding, an example in which the NMOS transistors M₂ andM_(bias) are equal in size will be described in connection with pointsdifferent from the comparative example. If the input impedance Z_(in) isequal to that in the comparative example, and the NMOS transistors M₂and M_(bias) are equal in size, as can be seen from Equations (1) and(3), g_(m2) of the present embodiment is as((1+g_(m1)Z_(L))/(1+2g_(m1)Z_(L))) times as g_(m2) of the comparativeexample. Therefore, if g_(m1)Z_(L) is sufficiently large, it is possibleto realize matching by using g_(m2) that is about half of that in thecomparative example. That is, in the above condition, it is possible torealize matching by using the NMOS transistor M₂ whose size is abouthalf of that in the comparative example. At this time, the bias currentflowing to the NMOS transistors M₂ and M_(bias) is about half of that inthe comparative example, and thus the size of the NMOS transistorM_(bias) can be about half. As described above, as g_(m2) decreases, theparasitic capacitance of the input node (the input terminal IN)decreases. For the NMOS transistor M_(bias), since a signal is merelyinput to the transistor originally used as the current source, theparasitic capacitance of the input node does not increase.

Further, the NMOS transistors M₂ and M_(bias) connected to the inputnode act as the noise source, but since their size can be reduced asdescribed above, g_(m2) and g_(mbias) can be half of a value of thecomparative example, thereby reducing the noise.

As described above, according to the present embodiment, the signalhaving the phase reverse to the output signal V_(out) is input to thegate of the transistor M_(bias) used as the bias current source of thecommon drain circuit as the feedback path. Therefore, it is possible toincrease a feedback signal (a negative feedback signal) without adding atransistor. As a result, even though g_(m2) of the NMOS transistor M₂ issmaller than that in the comparative example, the same input impendenceas in the comparative example is obtained. Therefore, since the sizes ofthe NMOS transistors M₂ and M_(bias) can be smaller than the sizes ofthose in the comparative example, the parasitic capacitance of the inputterminal IN can be reduced. Further, since g_(m2) and g_(mbias) can besmaller than those in the comparative example, the noise can be reduced.

The example in which the NMOS transistors M₂ and M_(bias) are equal insize has been described above, but even when the NMOS transistors M₂ andM_(bias) are different in size, the above-described effect is obtained.

Second Embodiment

The present embodiment relates to a circuit in which two low noiseamplifies of the first embodiment are connected in parallel to provide adifferential configuration.

FIG. 5 is a circuit diagram of a low noise amplifier according to asecond embodiment of the present invention. As illustrated in FIG. 5,the low noise amplifier includes an NMOS transistor M₁, an NMOStransistor M₂, an NMOS transistor M_(bias1) a load Z_(L1), an NMOStransistor M₃, an NMOS transistor M₄, an NMOS transistor M_(bias2), aload Z_(L2), a capacitor C₁ (a first capacitor), and a capacitor C₂ (asecond capacitor).

An input terminal IN₁ is connected to a gate of the NMOS transistor M₁,a source of the NMOS transistor M₂, and a drain of the NMOS transistorM_(bias1). A source of the NMOS transistor M₁ is connected to a groundpotential VSS, and a drain thereof is connected to an output terminalOUT₁, a gate of the NMOS transistor M₂, and one terminal of the loadZ_(L1). The other terminal of the load Z_(L1) is connected to apower-supply potential VDD. A drain of the NMOS transistor M₂ isconnected to the power-supply potential VDD. A gate of the NMOStransistor M_(bias1) is connected to an output terminal OUT₂ through thecapacitor C₁, and a source thereof is connected to the ground potentialVSS.

An input terminal IN₂ is connected to a gate of the NMOS transistor M₃,a source of the NMOS transistor M₄, and a drain of the NMOS transistorM_(bias2). A source of the NMOS transistor M₃ is connected to the groundpotential VSS, and a drain thereof is connected to the output terminalOUT₂, a gate of the NMOS transistor M₄, and one terminal of the loadZ_(L2). The other terminal of the load Z_(L2) is connected to thepower-supply potential VDD. A drain of the NMOS transistor M₄ isconnected to the power-supply potential VDD. A gate of the NMOStransistor M_(bias2) is connected to the output terminal OUT₁ throughthe capacitor C₂, and a source thereof is connected to the groundpotential VSS.

The NMOS transistors M₁, M₂, and M_(bias1) configure a first low noiseamplifier, and the NMOS transistors M₃, M₄, and M_(bias2) configure asecond low noise amplifier.

A bias voltage is applied to the gates of the NMOS transistors M_(bias1)and M_(bias2) so that the NMOS transistors M₁, M₂, M₃, M₄, M_(bias1),and M_(bias2) can operate in the saturated region.

The input impedances of the input terminals IN₁ and IN₂ arepower-matched with the signal source impedance in a predeterminedbandwidth. The input signal V_(in) input to the input terminal IN₁ isamplified with low noise, and an output signal V_(out) is output fromthe output terminal OUT₁. A signal having a phase reverse to an inputsignal V_(in) input to the input terminal IN₂ is amplified with lownoise, and a signal having a phase reverse to the output signal V_(out)is output from the output terminal OUT₂.

The signal having the phase reverse to the output signal V_(out) in thesecond low noise amplifier is input to the gate of the NMOS transistorM_(bias1) in the first low noise amplifier. The output signal V_(out) inthe first low noise amplifier is input to the gate of the NMOStransistor M_(bias2) in the second low noise amplifier.

The NMOS transistors M₁, M₂, and M_(bias1) and the NMOS transistors M₃,M₄, and M_(bias2) operate in the same manner as in the first embodiment,and thus description thereof will not be repeated.

As described above, since the differential configuration is providedusing the two low noise amplifiers of the first embodiment, the signalhaving the reverse phase can be easily input to the NMOS transistorsM_(bias1) and M_(bias2) by inputting the reverse phase side outputsignal.

Next, a characteristic comparison between a low noise amplifier of thepresent embodiment and a circuit in which a differential configurationis provided by a low noise amplifier of a comparative example will bedescribed. Here, the comparison is made using comparative circuits inwhich the sizes of transistors are adjusted so that the both circuitscan be equal in input impedance and gain.

FIG. 6( a) is a circuit diagram of a comparative circuit of a low noiseamplifier according to the second embodiment of the present invention.FIG. 6( b) is a circuit diagram of a comparative circuit of a low noiseamplifier according to the comparative example. For easy understanding,only one side of the differential configuration is illustrated in FIGS.6( a) and 6(b).

In each of the comparative circuits of FIGS. 6( a) and 6(b), a resistorR is used as a load, and an NMOS transistor M_(c) is cascode-connectedbetween the resistor R and a drain of the NMOS transistor M₁. A biasvoltage V_(bias1) is applied to the gate of the NMOS transistor M_(c). Abias voltage V_(bias2) is applied to gates of NMOS transistors M_(bias1)and M_(bias12).

Similarly to the first embodiment, when the input impedance of thecircuit of the present embodiment is equal to that of the circuit of thecomparative example, the mutual conductance of the common drain circuit(an NMOS transistor M₂₁) as the feedback path in the circuit of thepresent embodiment can be smaller than that of the circuit of thecomparative example. Here, the NMOS transistors M₂₁ and M_(bias11) areequal in size, and the NMOS transistors M₂₂ and M_(bias12) are equal insize. In this condition, the mutual conductance g_(m2) of each of theNMOS transistors M₂₁ and M_(bias11) is about half of the mutualconductance 2g_(m2) of each of the NMOS transistors M₂₂ and M_(bias12),so that a channel width of each of the NMOS transistors M₂₁ andM_(bias11) is about half of a channel width of each of the NMOStransistors M₂₂ and M_(bias12). In FIGS. 6( a) and 6(b), correspondingNMOS transistors have the almost same bias voltage, and a bias currentflowing through the NMOS transistors M₂₁ and M_(bias11) is about half ofa bias current flowing through the NMOS transistors M₂₂ and M_(bias12).As will be described later, in the above-described condition, the bothcircuits are the almost same in input impedance and gain.

Further, as described in FIG. 5, in the present embodiment, a gate of anNMOS transistor M_(bias11) (not shown) as well as the gate of the NMOStransistor M₂₁ is connected to an output node (that is, the outputterminal OUT₁). However, since the sizes of the NMOS transistors M₂₁ andM_(bias11) are about half of the sizes of the NMOS transistor M₂₂ of thecomparative example, a capacitance as a load of an output does notchange.

The other configuration is the same as in FIG. 5, and thus like partsare designated by like reference numerals, and description thereof willnot be repeated.

Next, simulation results of the comparative circuits of FIGS. 6( a) and6(b) will be described.

FIGS. 7( a) to FIG. 7( d) are views illustrating characteristics of thelow noise amplifier according to the second embodiment of the presentinvention and the low noise amplifier according to the comparativeexample. FIG. 7( a) is a Smith chart illustrating an input impedanceS11. FIG. 7( b) illustrates a voltage standing wave ratio (VSWR) of aninput. FIG. 7( c) illustrates a noise figure (NF). FIG. 7( d)illustrates a gain 521. In FIGS. 7( b) to 7(d), a horizontal axisindicates a frequency.

As can be seen in FIGS. 7( a) to 7(d), in the condition in which thegain and the input impedance are matched, in the present embodiment, theNF is improved compared to the comparative example. For example, at afrequency of 2.5 GHz, the NF is improved from 2.257 dB to 2.024 dB.

Further, since the sizes of the NMOS transistors M₂₁ and M_(bias11) arehalf of the sizes of the NMOS transistors M₂₂ and M_(bias12), theparasitic capacitance of an input is reduced.

As described above, according to the present embodiment, since the lownoise amplifiers of the first embodiments are connected to provide thedifferential configuration, the signal having the reverse phase can beeasily input to the NMOS transistors M_(bias1) and M_(bias2) byinputting the respective reverse phase side output signals.

Further, the same effects as in the first embodiment are obtained.

The embodiments of the present invention have been described in detail,but the concrete configuration is not limited to the above-describedembodiments, and various modifications may be made without departingfrom the spirit and scope of the present invention.

For example, a PMOS transistor may be used instead of an NMOStransistor.

For example, as a modification of the first embodiment, as illustratedin FIG. 8, a low noise amplifier may be configured with PMOS transistorsM_(p1), M_(p2), and M_(pbias). The circuit of FIG. 8 operates in thesame manner as in the first embodiment, and the same effects as in thefirst embodiment are obtained.

Further, as a modification of the second embodiment, as illustrated inFIG. 9, a low noise amplifier may be configured with PMOS transistorsM_(p1), M_(p2), M_(pbias1), M_(p3), M_(p4), and M_(pbias2). The circuitof FIG. 9 operates in the same manner as in the second embodiment, andthe same effects as in the second embodiment are obtained.

In the modification of the first embodiment and the modification of thesecond embodiment, a ground potential VSS is used as a first potential,and a power-supply potential VDD is used as a second potential.

Further, as the amplifier configured with the NMOS transistor M₁ and theload Z_(L), any circuit having a configuration other than theabove-described embodiments may be used. For example, even in the firstembodiment, similarly to the comparative circuit of the secondembodiment, an NMOS transistor M_(c) may be cascode-connected betweenthe load Z_(L) and the drain of the NMOS transistor M₁.

Further, a resistor or an inductor may be used as the loads Z_(L),Z_(L1), and Z_(L2).

The signal, which has the phase reverse to the output signal V_(out),input to the gate of the NMOS transistor M_(bias) in the firstembodiment may be generated by various methods (circuits), which will bedescribed below in third to sixth embodiments.

Third Embodiment

FIG. 10( a) is a circuit diagram of a single ended to differentialconversion circuit according to a third embodiment of the presentinvention. The circuit is an example of a circuit that generates asignal having a phase reverse to an output signal V_(out) by using adevice having a single ended to differential conversion function such asa transformer.

An input terminal IN is connected to a gate of an NMOS transistor M₁,and a drain of the NMOS transistor M₁ is connected to a first terminalat a primary side of a transformer I₁ (a signal conversion section). Asecond terminal at the primary side of the transformer I₁ is connectedto a power-supply potential VDD, and the primary side of the transformerI₁ functions as a load of an amplifier. At a secondary side of thetransformer I₁ a first terminal is connected to an output terminal OUT₁,and a second terminal is connected to an output terminal OUT₂. A middlepoint at the secondary side of the transformer I₁ is connected to aground potential VSS. A signal having the same phase as a signal V_(x)at a node X appears at the first terminal (OUT₁) at the secondary sideof the transformer I₁ and a signal having a phase reverse to the signalV_(x) appears at the second terminal (OUT₂).

FIG. 10( b) is a circuit diagram of a low noise amplifier according tothe third embodiment of the present invention.

The circuit is a circuit that generates a signal having a phase reverseto the output signal V_(out) in the first embodiment and an example inwhich the circuit of FIG. 10( a) is applied. The low noise amplifier ofFIG. 10( b) is configured so that an output signal V_(out), which hasthe same phase as a signal V_(x) at a node X, appeared at the firstterminal at the secondary side of the transformer I₁ is input to a gateof an NMOS transistor M₂, and a signal, which has a phase reverse to theoutput signal V_(out), appeared at the second terminal at the secondaryside of the transformer I₁ is input to a gate of an NMOS transistorM_(bias). The other configuration is the same as in FIG. 4 in the firstembodiment, and thus like parts are designated by like referencenumerals, and description thereof will not be repeated.

Further, instead of the transformer I₁ a different circuit componenthaving a single ended to differential conversion function may be used.

Fourth Embodiment

The amplifier itself may have the single ended to differentialconversion function.

FIG. 11( a) is a circuit diagram illustrating a single ended todifferential conversion circuit according to a fourth embodiment of thepresent invention. The single ended to differential conversion circuitis an example of a circuit in which a common source circuit and commongate circuit are combined in parallel. An input terminal IN is connectedto a gate of an NMOS transistor M₁ and a source of an NMOS transistorM_(3a). A drain of the NMOS transistor M₁ is connected to a load Z_(L)and an output terminal OUT₁. A drain of the NMOS transistor M_(3a) isconnected to a load Z_(L3a) and an output terminal OUT₂. A currentsource I_(1a) is connected between a source of the NMOS transistorM_(3a) and a ground potential VSS. A bias voltage is applied to gates ofthe NMOS transistors M₁ and M_(3a) so that the NMOS transistors M₁ andM_(3a) can operate in the saturated region. The NMOS transistor M_(3a)and the load Z_(L3a) act as a common gate amplifier. Therefore, a signalappeared at the drain of the NMOS transistor M_(3a) has a phase reverseto a signal appeared at the drain of the NMOS transistor M₁ thatoperates as a common source amplifier. Therefore, an output signalV_(out) and a signal having a phase reverse to the output signal V_(out)can be obtained.

A low noise amplifier to which the circuit of FIG. 11( a) is applied, asthe circuit that generates the signal having the phase reverse to theoutput signal V_(out) in the first embodiment, is configured as follows.

FIG. 11( b) is a circuit diagram of a low noise amplifier according tothe fourth embodiment of the present invention. As illustrated in FIG.11( b), the low noise amplifier includes the common gate circuit of FIG.11( a) including the transistor M_(3a), the load Z_(L3a), and thecurrent source I_(1a) in addition to the configuration of the low noiseamplifier of the first embodiment. The output terminal OUT₂ is connectedto the gate of the NMOS 11(a) and FIG. 4 in the first embodiment, andthus like parts are designated by like reference numerals, anddescription thereof will not be repeated.

Fifth Embodiment

FIG. 12( a) is a circuit diagram of a single ended to differentialconversion circuit according to a fifth embodiment of the presentinvention. The single ended to differential conversion circuit is anexample of a circuit using a differential amplifier. An input terminalIN is connected to a gate of an NMOS transistor M₁, and a source of theNMOS transistor M₁ and a source of an NMOS transistor M_(3b) (a fourthtransistor) are connected to one terminal of a current source I_(1b) (afirst current source). The other terminal of the current source I_(1b)is connected to a ground potential VSS. A drain of the NMOS transistorM₁ is connected to a load Z_(L) and an output terminal OUT₁. A drain ofthe NMOS transistor M_(3b) is connected to a load Z_(L3b) (a secondload) and an output terminal OUT₂. A bias voltage is applied to gates ofthe NMOS transistors M₁ and M_(3b) so that the NMOS transistors M₁ andM_(3b) can operate in the saturated region. The NMOS transistors M₁ andM_(3b), the current source I_(1b), and the loads Z_(L) and Z_(L3b)configure the differential amplifier, and the gate of the transistorM_(3b) is AC coupled to ground through a capacitor C_(1b). Since a sumof a current flowing to the NMOS transistor M₁ and a current flowing tothe NMOS transistor M_(3b) is determined by the current source I_(1b),when a current flowing to a node X decreases and an electric potentialat the node X is raised, a current flowing to a node Y increases, and anelectric potential at the node Y drops. The electric potential at thenode X and the electric potential at the node Y are always in a reversephase relationship, and thus an output signal V_(out) and a signalhaving a phase reverse to the output signal V_(out) can be obtained.

A low noise amplifier to which the circuit of FIG. 12( a) is applied, asthe circuit that generates the signal having the phase reverse to theoutput signal V_(out) in the first embodiment, is configured as follows.

FIG. 12( b) is a circuit diagram of a low noise amplifier according tothe fifth embodiment of the present invention. As illustrated in FIG.12( b), the low noise amplifier includes a current source I_(1b) betweenthe source of the NMOS transistor M₁ and the ground potential VSS in thelow noise amplifier of the first embodiment. The low noise amplifierfurther includes a part of the differential amplifying circuit includingthe transistor M_(3b), the load Z_(L3b), and the capacitor C_(1b) ofFIG. 12( a). The output terminal OUT₂ is connected to the gate of theNMOS transistor M_(bias). The other configuration is the same as in FIG.12( a) and FIG. 4 in the first embodiment, and thus like parts aredesignated by like reference numerals, and description thereof will notbe repeated.

For example, the NMOS transistor M₁ and the load Z_(L) in the circuit ofFIG. 12( a) are the same as the NMOS transistor M₁ and the load Z_(L)that configure the amplifier of the first embodiment of FIG. 4.

Sixth Embodiment

FIG. 13( a) is a circuit diagram of a single ended to differentialconversion circuit according to a sixth embodiment of the presentinvention. The single ended to differential conversion circuit is anexample of a circuit using a cascade-connection of a common sourcecircuit. An input terminal IN is connected to a gate of an NMOStransistor M₁. A source of the NMOS transistor M₁ and a source of anNMOS transistor M_(3c) (a fifth transistor) are connected to a groundpotential VSS. A drain of the NMOS transistor M₁ is connected to a loadZ_(L) and an output terminal OUT₁. A drain of the NMOS transistor M_(3c)is connected to a load Z_(L3c) (a third load) and an output terminalOUT₂. The drain of the NMOS transistor M₁ is connected to one terminalof a capacitor C_(1c) that cuts a direct current. The other terminal ofthe capacitor C_(1c) is connected to the gate of the transistor M_(3c).A bias voltage is applied to the gates of the NMOS transistors M₁ andM_(3c) so that the NMOS transistors M₁ and M_(3c) can operate in thesaturated region. Since a signal appeared at a node X is reversed by thecommon source circuit including the NMOS transistor M_(3c) and the loadZ_(L3C), an output signal V_(out) and a signal having a phase reverse tothe output signal V_(out) can be obtained.

A low noise amplifier to which the circuit of FIG. 13( a) is applied, asthe circuit that generates the signal having the phase reverse to theoutput signal V_(out) in the first embodiment, is configured as follows.

FIG. 13( b) is a circuit diagram of a low noise amplifier according tothe sixth embodiment of the present invention. As illustrated in FIG.13( b), the low noise amplifier includes a common source circuitincluding the transistor M_(3c), the load Z_(L3c), and the capacitorC_(1c) of FIG. 13( a) in addition to the configuration of the low noiseamplifier of the first embodiment. The output terminal OUT₂ is connectedto the gate of the NMOS transistor M_(bias). The other configuration isthe same as in FIG. 13( a) and FIG. 4 in the first embodiment, and thuslike parts are designated by like reference numerals, and descriptionthereof will not be repeated.

For example, the NMOS transistor M₁ and the load Z_(L) in the circuit ofFIG. 13( a) are the same as the NMOS transistor M₁ and the load Z_(L)that configure the amplifier in the first embodiment of FIG. 4.

Even in the third to sixth embodiments, the same effects as in the firstembodiment are obtained.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel methods and systems describedherein may be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the methods andsystems described herein may be made without departing from the spiritof the inventions. The accompanying claims and their equivalents areintended to cover such forms or modifications as would fall within thescope and spirit of the inventions.

1. A semiconductor integrated circuit device, comprising: an amplifiercomprising an input terminal and an output terminal, the input terminalreceiving an input signal, and the output terminal outputting an outputsignal; and a feedback circuit comprising a first transistor generatinga bias current, the feedback circuit being configured to operate basedon the bias current, and the feedback circuit being configured toreceive the output signal to supply a feedback signal to the inputterminal, wherein a signal having a reverse phase to the output signalis input to a gate of the first transistor.
 2. The semiconductorintegrated circuit device according to claim 1, wherein the feedbackcircuit further comprises a second transistor, the second transistorcomprising a gate receiving the output signal, a source connected to theinput terminal, and a drain connected to a first potential, the secondtransistor having the same conductivity type as the first transistor,and a bias voltage is additionally applied to the gate of the firsttransistor, the first transistor comprising a source connected to asecond potential and a drain connected to the input terminal.
 3. Thesemiconductor integrated circuit device according to claim 1, whereinthe amplifier comprises: a third transistor comprising a gate connectedto the input terminal, a source connected to a second potential, and adrain connected to the output terminal, the third transistor having thesame conductivity type as the first transistor; and a first loadconnected between the drain of the third transistor and a firstpotential.
 4. The semiconductor integrated circuit device according toclaim 1 wherein the amplifier comprises: a third transistor comprising agate connected to the input terminal and a source connected to a secondpotential, the third transistor having the same conductivity type as thefirst transistor; and a signal conversion section including a primarycircuit and a secondary circuit, the signal conversion section outputs asignal having the same phase as a signal applied to a first terminal ofthe primary circuit, via a first terminal of the secondary circuit, andoutputs a signal having a reverse phase to a signal applied to the firstterminal of the primary circuit, via a second terminal of the secondarycircuit, the first terminal of the primary circuit is connected to thedrain of the third transistor, a second terminal of the primary circuitis connected to the first potential, the first terminal of the secondarycircuit is connected to the output terminal, and the second terminal ofthe secondary circuit is connected to the gate of the first transistor.5. The semiconductor integrated circuit device according to claim 3,further comprising: a common gate circuit configured to amplify theinput signal to supply the amplified signal to the gate of the firsttransistor, as the signal having the reverse phase to the output signal.6. The semiconductor integrated circuit device according to claim 3,further comprising: a first current source connected between the sourceof the third transistor and the second potential; a fourth transistorcomprising a source connected to the source of the third transistor, thefourth transistor having the same conductivity type as the thirdtransistor; a capacitor connected between a gate of the fourthtransistor and the second potential; and a second load connected betweena drain of the fourth transistor and the first potential, wherein thedrain of the fourth transistor is connected to the gate of the firsttransistor.
 7. The semiconductor integrated circuit device according toclaim 3, further comprising: a fifth transistor comprising a sourceconnected to the second potential, the fifth transistor having the sameconductivity type as the third transistor; a capacitor connected betweena gate of the fifth transistor and the drain of the third transistor;and a third load connected between a drain of the fifth transistor andthe first potential, wherein the drain of the fifth transistor isconnected to the gate of the first transistor.
 8. The semiconductorintegrated circuit device according to claim 3, wherein the amplifiercomprises a cascode transistor, the cascode transistor comprising a gateto which a cascode bias voltage is applied, a source connected to thedrain of the third transistor, and a drain connected to the first load.9. The semiconductor integrated circuit device according to claim 1,wherein the feedback circuit further comprises a second transistor, thesecond transistor comprising a gate receiving the output signal, asource connected to the input terminal, and a drain connected to a firstpotential, the second transistor having the same conductivity type asthe first transistor, a bias voltage is additionally applied to the gateof the first transistor, the first transistor comprising a sourceconnected to a second potential and a drain connected to the inputterminal, and the amplifier comprises: a third transistor comprising agate connected to the input terminal, a source connected to the secondpotential, and a drain connected to the output terminal, the thirdtransistor having the same conductivity type as the first transistor;and a first load connected between the drain of the third transistor andthe first potential.
 10. The semiconductor integrated circuit deviceaccording to claim 9 wherein the first transistor, the secondtransistor, and the third transistor are N-type MOS transistors, thefirst potential is a power-supply potential, and the second potential isa ground potential.
 11. The semiconductor integrated circuit deviceaccording to claim 9, wherein the first transistor, the secondtransistor, and the third transistor are P-type MOS transistors, thefirst potential is a ground potential, and the second potential is apower-supply potential.
 12. The semiconductor integrated circuit deviceaccording to claim 9, wherein the bias voltage applied to the gate ofthe first transistor is set so that the first transistor, the secondtransistor, and the third transistor operate in a saturated region. 13.The semiconductor integrated circuit device according to claim 1,wherein the feedback circuit is a common drain circuit.
 14. Thesemiconductor integrated circuit device according to claim 1, whereinthe input signal is input to the input terminal from a signal source andan input impedance of the input terminal is power-matched with animpedance of the signal source.
 15. A semiconductor integrated circuitdevice, comprising: a first semiconductor integrated circuit deviceaccording to claim 1; and a second semiconductor integrated circuitdevice according to claim 1, wherein the output signal in the secondsemiconductor integrated circuit device is input to the gate of thefirst transistor in the first semiconductor integrated circuit device,as the signal having the reverse phase to the output signal, and theoutput signal in the first semiconductor integrated circuit device isinput to the gate of the first transistor in the second semiconductorintegrated circuit device, as the signal having the reverse phase to theoutput signal.
 16. The semiconductor integrated circuit device accordingto claim 15, further comprising: a first capacitor connected between thegate of the first transistor in the first semiconductor integratedcircuit device and the output terminal in the second semiconductorintegrated circuit device; and a second capacitor connected between thegate of the first transistor in the second semiconductor integratedcircuit device and the output terminal in the first semiconductorintegrated circuit device.
 17. The semiconductor integrated circuitdevice according to claim 15, wherein the input signal in the firstsemiconductor integrated circuit device has a reverse phase to the inputsignal in the second semiconductor integrated circuit device.
 18. Thesemiconductor integrated circuit device according to claim 17, whereinthe input terminal in the first semiconductor integrated circuit deviceand the input terminal in the second semiconductor integrated circuitdevice are connectable to a signal source, and input impedances of theinput terminal in the first semiconductor integrated circuit device andthe input terminal in the second semiconductor integrated circuit deviceare power-matched with an impedance of the signal source.
 19. Asemiconductor integrated circuit device, comprising: a firstsemiconductor integrated circuit device according to claim 9; and asecond semiconductor integrated circuit device according to claim 9,wherein the output signal in the second semiconductor integrated circuitdevice is input to the gate of the first transistor in the firstsemiconductor integrated circuit device, as the signal having thereverse phase to the output signal, and the output signal in the firstsemiconductor integrated circuit device is input to the gate of thefirst transistor in the second semiconductor integrated circuit device,as the signal having the reverse phase to the output signal.
 20. Acommunication system, comprising: a low noise amplifier configured toamplify a radio signal to output an output signal, the radio signalbeing received by an antenna, wherein the low noise amplifier comprises:an amplifier comprising an input terminal and an output terminal, theinput terminal receiving the radio signal, and the output terminaloutputting the output signal; and a feedback circuit comprising a firsttransistor generating a bias current, the feedback circuit beingconfigured to operate based on the bias current, and the feedbackcircuit being configured to receive the output signal to supply afeedback signal to the input terminal, a signal having a reverse phaseto the output signal is input to a gate of the first transistor.